TTL SVGA Horizontal Signals

Electric Lunatic

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TTL SVGA
Horizontal Signals

Synch, Blanking and Horizontal Line Clock

Horizontal Signals Generator Circuit Schematic

As stated in the introduction, this circuit was inspired by an SVGA project by Ben Eater. The horizontal signals generator is not a verbatim copy of Ben's circuit but is very similar. A link to Ben Eater's SVGA board project is here : https://www.eater.net/vga

Horizontal Signals Timing

The diagram shown above illustrates the timing of the horizontal synchronization and blanking signals in relation to the horizontal signals generator circuit.

Circuit Description

Horizontal timing is generated by three 74LS193 binary counters connected in tandem. The first counter is clocked with a 20 MHz source. The Q0 output of the first counter supplies the 10 MHz signal used to generate the RGB video signal. The outputs Q1, Q2 and Q3 are used for both generating the RGB video signal and horizontal timing. Q0 through Q3 from the second counter and Q0 through Q1 from the third counter are used both for generating the video memory column address and horizontal timing.

A 3 input NOR gate, inverters and 8 input NAND gates are connected to make four identity detectors that generate the start and stop pulses of the horizontal synch pulse and horizontal blanking period. The 3 input NOR gate consolidates the Q1 and Q3 outputs of the first counter as they are always 0 for all four generated pulses.

Four NAND gates are used to make two RS latches, which generate the horizontal synch and horizontal blanking period signals. In this circuit, the 74LS00 can be used for the RS latches, but I chose to use the 74F00 to tighten up the timing a bit.

The pulse indicating the end of the horizontal blanking period is also used to clock the vertical signal generate and is labeled LINE CLOCK .

Note that the 74LS244 buffer that drives the video memory column address is in high-Z mode during both horizontal and vertical blanking periods. This is to allow the host CPU to access video memory during the vertical blanking period.

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